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Implemented 64-bit paging
This commit is contained in:
+38
-20
@@ -1,37 +1,55 @@
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#ifndef _PAGING_H
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#define _PAGING_H
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#include <bootloader.h>
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#include <kernel.h>
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#define PTE_FLAG_PRESENT (1ULL << 0) // Page is present in the table
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#define PTE_FLAG_WRITE (1ULL << 1) // Read-write
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#define PTE_FLAG_USER (1ULL << 2) // User-mode (DPL3) access allowed
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#define PTE_FLAG_PWT (1ULL << 3) // Page write-thru
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#define PTE_FLAG_NOCACHE (1ULL << 4) // Cache disable
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#define PTE_FLAG_ACCESSED (1ULL << 5) // Indicates whether page was accessed
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#define PTE_FLAG_DIRTY (1ULL << 6) // Page size (valid for PD and PDPT only)
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#define PTE_FLAG_PAT (1ULL << 7) // Page Attribute Table (valid for PT only)
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#define PTE_FLAG_GLOBAL (1ULL << 8) // Indicates the page is globally cached
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#define PTE_FLAG_SHARED (1ULL << 9) // Userland page is shared
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#define PTE_FLAG_NOEXEC (1ULL << 63) // No execute
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#define PTE_FLAG_PRESENT (1UL << 0) // Page is present in the table
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#define PTE_FLAG_WRITE (1UL << 1) // Read-write
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#define PTE_FLAG_USER (1UL << 2) // User-mode (DPL3) access allowed
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#define PTE_FLAG_PWT (1UL << 3) // Page write-thru
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#define PTE_FLAG_NOCACHE (1UL << 4) // Cache disable
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#define PTE_FLAG_ACCESSED (1UL << 5) // Indicates whether page was read/written
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#define PTE_FLAG_DIRTY (1UL << 6) // Indicates whether page was written to (valid for PT only)
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#define PTE_FLAG_PAT (1UL << 7) // Page Attribute Table (valid for PT only)
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#define PTE_FLAG_PAGESIZE (1UL << 7) // Page size (valid for PD and PDPT only)
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#define PTE_FLAG_RSVD (1UL << 7) // No idea (valid for PML4 and PML5 only)
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#define PTE_FLAG_GLOBAL (1UL << 8) // Global caching or sum (valid for PT only)
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#define PTE_FLAG_NOEXEC (1UL << 63) // No execute (the XD bit)
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// Region caching according to the Limine protocol
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#define PTE_FLAG_CACHE (PTE_FLAG_PWT | PTE_FLAG_PAT)
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#define PTE_ADDR_MASK 0x000FFFFFFFFFFFFFF000ULL
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#define PTE_ADDR(_pte) ((_pte) & PAGE_ADDR_MASK)
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#define PTE_ADDR_MASK 0x000FFFFFFFFFF000UL
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#define PTE_ADDR(_pte) ((_pte) & PTE_ADDR_MASK)
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#define PML4_IDX(_ptr) (((_ptr) >> 39) & 0x1FFUL)
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#define PDPT_IDX(_ptr) (((_ptr) >> 30) & 0x1FFUL)
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#define PD_IDX(_ptr) (((_ptr) >> 21) & 0x1FFUL)
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#define PT_IDX(_ptr) (((_ptr) >> 12) & 0x1FFUL)
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#define TO_VIRT(_ptr) ((void*)((uintptr_t)(_ptr) + bootloader.hhdm_offset))
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#define TO_PHYS(_ptr) ((void*)((uintptr_t)(_ptr) - bootloader.hhdm_offset))
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#define PAGE_SIZE 0x1000
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#define PAGE_SIZE_LARGE 0x200000
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#define PAGE_SIZE_HUGE 0x40000000
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// From the Linux kernel source
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// WARN: This will only invalidate on one core
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static inline void pag_invalidate(size_t vaddr) { __asm__ volatile("invlpg (%0)" :: "r" (vaddr) : "memory"); }
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static inline void pag_invalidate(void* vaddr) { __asm__ volatile("invlpg (%0)" :: "r" (vaddr) : "memory"); }
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static inline bool pag_is_user_addr(void* vaddr) { return (uintptr_t)vaddr < 0x0000800000000000UL; }
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int pag_init(void);
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void pag_map(uint64_t* pml4, void* vaddr, void* paddr, uint64_t flags);
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void pag_unmap(uint64_t* pml4, void* vaddr);
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void pag_switch(uint64_t* pml4);
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uint64_t* pag_new_pml(void);
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// NOTE: All uint64_t* are VIRTUAL addresses
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int pag_init(void);
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uint64_t* pag_get_pte(uint64_t* pml4, void* vaddr);
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void pag_map(uint64_t* pml4, void* vaddr, void* paddr, uint64_t flags);
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void pag_map_region(uint64_t* pml4, void* vaddr, void* paddr, size_t count, uint64_t flags);
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void pag_unmap(uint64_t* pml4, void* vaddr);
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void pag_unmap_region(uint64_t* pml4, void* vaddr, size_t count);
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void pag_protect(uint64_t* pml4, void* vaddr, uint64_t flags);
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void* pag_get_phys(uint64_t* pml4, void* vaddr);
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void pag_set_pml4(uint64_t* pml4);
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uint64_t* pag_get_pml4(void);
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uint64_t* pag_get_next_tab(uint64_t* tab, offset_t index);
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uint64_t* pag_new_next_tab(uint64_t* tab, offset_t index);
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#endif
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+1
-4
@@ -34,10 +34,7 @@ void _start(void) {
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// Memory management
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if (pmm_init() != 0) panic("Failed to initalize Physical Memory Manager.");
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void* paddr = pmm_alloc();
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pmm_free(paddr);
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//if (pag_init() != 0) panic("Failed to initalize Paging.");
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if (pag_init() != 0) panic("Failed to initalize Paging.");
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//if (kmalloc_init() != 0) panic("Failed to initialize kernel heap.");
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// Tasking
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+180
-19
@@ -1,35 +1,196 @@
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#include "serial.h"
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#include <bootloader.h>
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#include <kernel.h>
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#include <limine.h>
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#include <string.h>
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#include <serial.h>
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#include <pmm.h>
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#include <paging.h>
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size_t* pag_globalpd = NULL;
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// VIRTUAL address of the kernels PML4
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uint64_t* pag_kernel_pml4 = NULL;
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void pag_invalidate(size_t vaddr) { __asm__ volatile ("invlpg %0" ::"m"(vaddr)); }
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int pag_init(void) {
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pag_kernel_pml4 = TO_VIRT(pmm_alloc());
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if (pag_kernel_pml4 == NULL) {
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debugf("[pag] Failed to allocate kernel PML4. Not enough memory.\n");
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return 1;
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}
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memset(pag_kernel_pml4, 0, PAGE_SIZE);
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int pag_init() {
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size_t pd_phys = 0;
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__asm__ volatile ("movq %%cr3, %0" : "=r"(pd_phys));
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if (!pd_phys) return 1;
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pag_map_region(
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pag_kernel_pml4,
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(void*)bootloader.kernel_virt_base,
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(void*)bootloader.kernel_phys_base,
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dceil(bootloader.executable->size, PAGE_SIZE),
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PTE_FLAG_WRITE | PTE_FLAG_PRESENT
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);
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size_t pd_virt = pd_phys + bootloader.hhdm_offset;
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pag_globalpd = (size_t*)pd_virt;
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for (size_t i = 0; i < bootloader.mm_entry_count; i++) {
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struct limine_memmap_entry* entry = bootloader.mm_entries[i];
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uint64_t flags = 0;
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switch (entry->type) {
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case LIMINE_MEMMAP_USABLE: flags = PTE_FLAG_WRITE; break;
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case LIMINE_MEMMAP_RESERVED: continue;
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case LIMINE_MEMMAP_ACPI_RECLAIMABLE: flags = PTE_FLAG_WRITE; break;
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case LIMINE_MEMMAP_ACPI_NVS: break;
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case LIMINE_MEMMAP_BAD_MEMORY: continue;
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case LIMINE_MEMMAP_BOOTLOADER_RECLAIMABLE: flags = PTE_FLAG_WRITE; break;
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case LIMINE_MEMMAP_EXECUTABLE_AND_MODULES: flags = PTE_FLAG_WRITE; break;
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case LIMINE_MEMMAP_FRAMEBUFFER: flags = PTE_FLAG_WRITE | PTE_FLAG_PWT; break;
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case LIMINE_MEMMAP_RESERVED_MAPPED: flags = 0; break;
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default:
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debugf(
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"[pag] %p - %p: Unknown memmap type %d. Will remain unmapped.\n",
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entry->base, entry->base + entry->length, entry->type
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);
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continue;
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}
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pag_map_region(
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pag_kernel_pml4,
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(void*)(entry->base + bootloader.hhdm_offset), (void*)entry->base,
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dceil(entry->length, PAGE_SIZE),
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flags | PTE_FLAG_PRESENT
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);
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}
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debugf("[pag] Switching to kernel PML4 at %p.\n", pag_kernel_pml4);
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pag_set_pml4(pag_kernel_pml4);
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debugf("[pag] Paging initialized.");
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return 0;
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}
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void pag_map(size_t vaddr, size_t paddr, size_t flags);
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size_t pag_umap(size_t vaddr);
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size_t pag_virt_to_phys(size_t vaddr);
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size_t* pag_get_pagedir();
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size_t* pag_get_task_pagedir(void* task);
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void pag_set_pagedir(size_t* pagedir);
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size_t* pag_alloc_pagedir();
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void pag_free_pagedir(size_t* pagedir);
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void pag_invalidate(size_t vaddr);
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uint64_t* pag_get_pte(uint64_t* pml4, void* vaddr) {
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uintptr_t v = (uintptr_t)vaddr;
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if (v % PAGE_SIZE != 0) {
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debugf("[pag] Could not get PTE from non-aligned virtual address %p.\n", vaddr);
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return NULL;
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}
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uint64_t* pdpt = pag_get_next_tab(pml4, PML4_IDX(v));
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if (pdpt == NULL) {
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debugf("[pag] Could not get PTE. %p was not found in PML4.\n");
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return NULL;
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}
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uint64_t* pd = pag_get_next_tab(pdpt, PDPT_IDX(v));
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if (pd == NULL) {
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debugf("[pag] Could not get PTE. %p was not found in PDPT.\n");
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return NULL;
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}
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uint64_t* pt = pag_get_next_tab(pd, PD_IDX(v));
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if (pt == NULL) {
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debugf("[pag] Could not get PTE. %p was not found in PD.\n");
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return NULL;
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}
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return &pt[PT_IDX(v)];
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}
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uint64_t* pag_new_pte(uint64_t* pml4, void* vaddr) {
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uintptr_t v = (uintptr_t)vaddr;
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if (v % PAGE_SIZE != 0) {
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debugf("[pag] Could not create PTE for non-aligned virtual address %p.\n", vaddr);
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return NULL;
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}
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uint64_t* pdpt = pag_new_next_tab(pml4, PML4_IDX(v));
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if (pdpt == NULL) {
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debugf("[pag] Failed to create PDPT. Not enough memory.\n");
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return NULL;
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}
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uint64_t* pd = pag_new_next_tab(pdpt, PDPT_IDX(v));
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if (pd == NULL) {
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debugf("[pag] Failed to create PD. Not enough memory.\n");
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if (pdpt != NULL) pmm_free(pdpt);
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return NULL;
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}
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uint64_t* pt = pag_new_next_tab(pd, PD_IDX(v));
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if (pt == NULL) {
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debugf("[pag] Failed to create PT. Not enough memory.\n");
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if (pd != NULL) pmm_free(pd);
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if (pdpt != NULL) pmm_free(pdpt);
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return NULL;
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}
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return &pt[PT_IDX(v)];
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}
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void pag_map(uint64_t* pml4, void* vaddr, void* paddr, uint64_t flags) {
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uintptr_t p = (uintptr_t)paddr;
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if (p % PAGE_SIZE != 0) {
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debugf("[pag] Could not map %p to %p. Physical address is not aligned.\n", paddr, vaddr);
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return;
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}
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uint64_t* page = pag_new_pte(pml4, vaddr);
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*page = PTE_ADDR(p) | flags | PTE_FLAG_PRESENT;
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pag_invalidate(vaddr);
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}
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void pag_map_region(uint64_t* pml4, void* vaddr, void* paddr, size_t count, uint64_t flags) {
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for (size_t i = 0; i < count; i++) {
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pag_map(pml4, vaddr + i * PAGE_SIZE, paddr + i * PAGE_SIZE, flags);
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}
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}
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// TODO: This is a pmm memory leak. If all pages in a PT are unmapped, remove
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// that PT from it's PD. This applies to PDs & PDPTs too.
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void pag_unmap(uint64_t* pml4, void* vaddr) {
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uint64_t* pte = pag_get_pte(pml4, vaddr);
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*pte = 0;
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pag_invalidate(vaddr);
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}
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void pag_unmap_region(uint64_t* pml4, void* vaddr, size_t count) {
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for (size_t i = 0; i < count; i++) {
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pag_unmap(pml4, vaddr + i * PAGE_SIZE);
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}
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}
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void pag_protect(uint64_t* pml4, void* vaddr, uint64_t flags) {
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uint64_t* pte = pag_get_pte(pml4, vaddr);
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*pte = PTE_ADDR(*pte) | flags | PTE_FLAG_PRESENT;
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}
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void* pag_get_phys(uint64_t* pml4, void* vaddr) {
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uint64_t* pte = pag_get_pte(pml4, vaddr);
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return (void*)PTE_ADDR(*pte);
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}
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void pag_set_pml4(uint64_t* pml4) {
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__asm__ volatile("mov %0, %%cr3" :: "r" (TO_PHYS(pml4)) : "memory");
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}
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uint64_t* pag_get_pml4(void) {
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uint64_t* pml4;
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__asm__ volatile("movq %%cr3, %0" : "=r"(pml4) :: "memory");
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return TO_VIRT(pml4);
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}
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uint64_t* pag_get_next_tab(uint64_t* tab, offset_t index) {
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if (index >= 512 || tab == NULL) return NULL;
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else if (tab[index] & PTE_FLAG_PRESENT) return TO_VIRT(tab[index] & PTE_ADDR_MASK);
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else return NULL;
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}
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uint64_t* pag_new_next_tab(uint64_t* tab, offset_t index) {
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if (tab == NULL) return NULL;
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uint64_t* vaddr = pag_get_next_tab(tab, index);
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if (vaddr != NULL) return vaddr;
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void* paddr = pmm_alloc();
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if (!paddr) {
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debugf("[pag] Failed to allocate page for new table.\n");
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return NULL;
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}
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vaddr = TO_VIRT(paddr);
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memset(vaddr, 0, PAGE_SIZE);
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tab[index] = (uintptr_t)paddr | PTE_FLAG_PRESENT | PTE_FLAG_WRITE | PTE_FLAG_USER;
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return vaddr;
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}
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