diff --git a/.history b/.history
index 45e8c0e..80a1924 160000
--- a/.history
+++ b/.history
@@ -1 +1 @@
-Subproject commit 45e8c0ea8719de8538ed062bcfa06838458dcb26
+Subproject commit 80a1924f3d59e0cf28b7e9fd7543c9139a334c25
diff --git a/synth_pcb-backups/synth_pcb-2026-04-29_170850.zip b/synth_pcb-backups/synth_pcb-2026-04-29_170850.zip
new file mode 100644
index 0000000..32a96e2
Binary files /dev/null and b/synth_pcb-backups/synth_pcb-2026-04-29_170850.zip differ
diff --git a/synth_pcb-backups/synth_pcb-2026-04-29_175508.zip b/synth_pcb-backups/synth_pcb-2026-04-29_175508.zip
new file mode 100644
index 0000000..97cfc95
Binary files /dev/null and b/synth_pcb-backups/synth_pcb-2026-04-29_175508.zip differ
diff --git a/synth_pcb-backups/synth_pcb-2026-04-29_175718.zip b/synth_pcb-backups/synth_pcb-2026-04-29_175718.zip
new file mode 100644
index 0000000..5d4e5ca
Binary files /dev/null and b/synth_pcb-backups/synth_pcb-2026-04-29_175718.zip differ
diff --git a/synth_pcb-backups/synth_pcb-2026-04-29_175738.zip b/synth_pcb-backups/synth_pcb-2026-04-29_175738.zip
new file mode 100644
index 0000000..715d79d
Binary files /dev/null and b/synth_pcb-backups/synth_pcb-2026-04-29_175738.zip differ
diff --git a/synth_pcb-backups/synth_pcb-2026-04-29_175804.zip b/synth_pcb-backups/synth_pcb-2026-04-29_175804.zip
new file mode 100644
index 0000000..87746ef
Binary files /dev/null and b/synth_pcb-backups/synth_pcb-2026-04-29_175804.zip differ
diff --git a/synth_pcb-backups/synth_pcb-2026-04-29_175917.zip b/synth_pcb-backups/synth_pcb-2026-04-29_175917.zip
new file mode 100644
index 0000000..3cef61b
Binary files /dev/null and b/synth_pcb-backups/synth_pcb-2026-04-29_175917.zip differ
diff --git a/synth_pcb-backups/synth_pcb-2026-04-29_181021.zip b/synth_pcb-backups/synth_pcb-2026-04-29_181021.zip
new file mode 100644
index 0000000..e7a403a
Binary files /dev/null and b/synth_pcb-backups/synth_pcb-2026-04-29_181021.zip differ
diff --git a/synth_pcb.kicad_pcb b/synth_pcb.kicad_pcb
index b4ebf3a..f90e9ca 100644
--- a/synth_pcb.kicad_pcb
+++ b/synth_pcb.kicad_pcb
@@ -1838,7 +1838,7 @@
 		(descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row")
 		(tags "Through hole pin header THT 1x02 2.54mm single row")
 		(property "Reference" "J9"
-			(at 0 -2.38 0)
+			(at 0 5 0)
 			(layer "F.SilkS")
 			(uuid "f1025ba9-6da4-4fed-aee8-19919d0ae4b6")
 			(effects
@@ -1848,15 +1848,15 @@
 				)
 			)
 		)
-		(property "Value" "POT +-"
-			(at -0.5 4.92 0)
-			(layer "F.Fab")
+		(property "Value" "POT_AND_BUTTON_PWR"
+			(at -2 1.5 90)
+			(layer "B.SilkS")
 			(uuid "e87f60e4-1983-4a76-b5c9-9218b880fea8")
 			(effects
 				(font
-					(size 1 1)
-					(thickness 0.15)
+					(size 0.5 0.5)
 				)
+				(justify mirror)
 			)
 		)
 		(property "Datasheet" ""
@@ -2560,7 +2560,7 @@
 		(descr "Mounting Hole 2.2mm, M2, generated by kicad-footprint-generator mountinghole.py")
 		(tags "mountinghole M2")
 		(property "Reference" "H2"
-			(at 0 -3.15 0)
+			(at 2.333274 -2.666726 0)
 			(layer "F.SilkS")
 			(uuid "13ace7eb-3201-42ea-8576-0b6604019889")
 			(effects
@@ -4454,7 +4454,7 @@
 		(descr "Mounting Hole 2.2mm, M2, generated by kicad-footprint-generator mountinghole.py")
 		(tags "mountinghole M2")
 		(property "Reference" "H4"
-			(at 0 -3.15 0)
+			(at -3.05 1.5 0)
 			(layer "F.SilkS")
 			(uuid "381c0d5e-d23a-410a-a73e-3ce4b28c4ff9")
 			(effects
@@ -7410,7 +7410,7 @@
 		(descr "Mounting Hole 2.2mm, M2, generated by kicad-footprint-generator mountinghole.py")
 		(tags "mountinghole M2")
 		(property "Reference" "H1"
-			(at 0 -3.15 0)
+			(at 3.5 -1.5 0)
 			(layer "F.SilkS")
 			(uuid "fd4ae31b-d2c2-4fc0-a333-458390861c95")
 			(effects
@@ -8050,6 +8050,18 @@
 		(layer "Edge.Cuts")
 		(uuid "cdaa7a6f-285f-4e83-948a-a8140b8df9ed")
 	)
+	(gr_text "WayWayWay"
+		(at 118 137 0)
+		(layer "F.SilkS")
+		(uuid "9a849f0e-f8ea-42c1-b957-4c2ee38fadea")
+		(effects
+			(font
+				(size 0.6 0.6)
+				(bold yes)
+			)
+			(justify left bottom)
+		)
+	)
 	(gr_text "Synth module\nby Záporáci:\n	Limit6\n	Osuku69\n	PoliEcho\n	Tom-on64"
 		(at 132.5 138 0)
 		(layer "F.SilkS")