forked from PoliEcho-holding-org/kern
57 lines
2.5 KiB
C
57 lines
2.5 KiB
C
#ifndef _PAGING_H
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#define _PAGING_H
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#include <bootloader.h>
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#include <kernel.h>
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#define PTE_FLAG_PRESENT (1UL << 0) // Page is present in the table
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#define PTE_FLAG_WRITE (1UL << 1) // Read-write
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#define PTE_FLAG_USER (1UL << 2) // User-mode (DPL3) access allowed
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#define PTE_FLAG_PWT (1UL << 3) // Page write-thru
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#define PTE_FLAG_NOCACHE (1UL << 4) // Cache disable
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#define PTE_FLAG_FETCH (1UL << 4) // Fetch
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#define PTE_FLAG_ACCESSED (1UL << 5) // Indicates whether page was read/written
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#define PTE_FLAG_DIRTY (1UL << 6) // Indicates whether page was written to (valid for PT only)
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#define PTE_FLAG_PAT (1UL << 7) // Page Attribute Table (valid for PT only)
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#define PTE_FLAG_PAGESIZE (1UL << 7) // Page size (valid for PD and PDPT only)
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#define PTE_FLAG_RSVD (1UL << 7) // No idea (valid for PML4 and PML5 only)
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#define PTE_FLAG_GLOBAL (1UL << 8) // Global caching or sum (valid for PT only)
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#define PTE_FLAG_NOEXEC (1UL << 63) // No execute (the XD bit)
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// Region caching according to the Limine protocol
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#define PTE_FLAG_CACHE (PTE_FLAG_PWT | PTE_FLAG_PAT)
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#define PTE_ADDR_MASK 0x000FFFFFFFFFF000UL
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#define PTE_ADDR(_pte) ((_pte) & PTE_ADDR_MASK)
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#define PML4_IDX(_ptr) (((_ptr) >> 39) & 0x1FFUL)
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#define PDPT_IDX(_ptr) (((_ptr) >> 30) & 0x1FFUL)
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#define PD_IDX(_ptr) (((_ptr) >> 21) & 0x1FFUL)
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#define PT_IDX(_ptr) (((_ptr) >> 12) & 0x1FFUL)
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#define TO_VIRT(_ptr) ((void*)((uintptr_t)(_ptr) + bootloader.hhdm_offset))
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#define TO_PHYS(_ptr) ((void*)((uintptr_t)(_ptr) - bootloader.hhdm_offset))
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#define PAGE_SIZE 4096
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#define PAGE_SIZE_LARGE 0x200000
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#define PAGE_SIZE_HUGE 0x40000000
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// WARN: This will only invalidate on one core
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static inline void pag_invalidate(void* vaddr) { __asm__ volatile("invlpg (%0)" :: "r" (vaddr) : "memory"); }
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static inline bool pag_is_user_addr(void* vaddr) { return (uintptr_t)vaddr < 0x0000800000000000UL; }
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// NOTE: All uint64_t* are VIRTUAL addresses
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int pag_init(void);
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uint64_t* pag_get_pte(uint64_t* pml4, void* vaddr);
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int pag_map(uint64_t* pml4, void* vaddr, void* paddr, uint64_t flags);
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int pag_map_region(uint64_t* pml4, void* vaddr, void* paddr, size_t count, uint64_t flags);
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int pag_unmap(uint64_t* pml4, void* vaddr);
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int pag_unmap_region(uint64_t* pml4, void* vaddr, size_t count);
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int pag_protect(uint64_t* pml4, void* vaddr, uint64_t flags);
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void* pag_get_phys(uint64_t* pml4, void* vaddr);
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void pag_set_pml4(uint64_t* pml4);
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uint64_t* pag_get_pml4(void);
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uint64_t* pag_get_next_tab(uint64_t* tab, offset_t index);
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uint64_t* pag_new_next_tab(uint64_t* tab, offset_t index);
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#endif
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